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HIP0063
PRELIMINARY
October 1995
Hex Low Side MOSFET Driver with Serial or Parallel Interface and Diagnostic Fault Control
Description
The HIP0063 is a logic controlled, six channel Low Side Power Driver. As shown in the Block Diagram, the outputs are controlled via the serial data interface or, by user option, each output may be independently controlled from the respective parallel input. In addition, PWM logic switching control (HLOS) may be directly applied to channels 0 and 1 in parallel, or channels 4 and 5 in parallel. Output fault conditions may be detected as an output load short to supply when the output is ON or as an open load/ground short when the output is OFF. If an over-current short exists at one output, gate drive goes to a low duty cycle mode. It will remain in the low duty cycle mode until switched off or the fault is cleared. Fault bits are sent to a fault register to indicate which channel is at fault. The fault bits are indicated by a logic one and is internally latched when CS goes low. A fault bit will return to zero when the fault disappears. Either an 8-bit or 16-bit SPI communication mode may be used. Refer to the application section for bit control information. Over-voltage shutdown protection for all outputs will occur when VPWR (Battery/ MOSFET Supply) exceeds 35V typical. When VCC is less than 3.5V, gate drive is switched off. The input and gate control logic is fully function when the VCC supply is greater than 4V typical. The HIP0063 has an internal drain-to-gate zener which is used to voltage clamp the output drain-to-source voltage of the MOSFET. The HIP0063 is fabricated in a Power BiMOS IC process, and is intended for use in automotive and other applications having a wide range of temperature and electrical stress conditions. It is particularly well suited for MOSFET control in circuits driving lamps, displays, relays, and solenoids in applications requiring low operating power.
Features
* Six Channel MOSFET Driver with Gate Drive Control by Serial (SPI) or Parallel Interface and an Option for PWM Logic Switching Control * Drain Monitor Provides Fault Detection and Voltage Clamp for Each Channel * Output Voltage Zener Clamp. . . . . . . . . . 67V Typ * 5V CMOS Logic Level Input Control * VCC Logic Level Power Supply - 5V VCC Logic Power Supply - Turns Off Gate Drive for Low or Loss of VCC * VPWR System Level Power Supply Management - 5.5V to 17V Battery/System Level Power Supply Monitor - Over-Voltage Shutdown . . . . . . . . . . . . 35V Typ * Output Supply/Load Short and Open Load/Ground Short Fault Detection * Automatic Change to Low Duty Cycle Drive Mode When Output Short-to-Supply Detected * Fault Diagnostic Feedback via the SPI Bus * Operating Temp Range . . . . . . . -40oC to +125oC
Applications
* * * * Automotive and Industrial Systems Control of Solenoids, Relays and Lamp Drivers Interface to Logic and P Controllers Robotic System Controller
Ordering Information
PART NUMBER HIP0063AB TEMPERATURE RANGE -40oC to +125oC PACKAGE 28 Lead Plastic SOIC (W)
Pinout
HIP0063 SOIC TOP VIEW
HLOS 1 HPW01 2 HPW45 3 P10 4 P11 5 P12 6 P13 7 P14 8 P15 9 CS 10 SO 11 SI 12 SCK 13 GND 14 28 VPWR 27 G0 26 D0 25 G1 24 D1 23 D2 22 G2 21 G3 20 D3 19 D4 18 G4 17 D5 16 G5 15 VCC
Block Diagram
+VPWR
VPWR VCC
OVSD +5V POR
CHANNEL#0 - (1 OF 6) FAULT LOGIC AND LATCH F0 FAULT DATA OVSD TG GATE CONTROL LOGIC
D0 (DRAIN MONITOR VOLT,VDM) G0 (GATE DR. VOLT.,VG) GND
HPW01 HPW45 HLOS CS SI SO SCK PI0-5
MUX PWM CONTROL S0 S6 P0 SPI (SER.) CONTROL S0-5 F0-5 (6) PI0-5
TG
POR HIP0063
OSC AND TIME DELAY CONTROL
EXT POWER MOSFET AND TYP LOAD
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
File Number
4009
1
HIP0063
VCC 5V
VPWR 14V
S0 SI SCK CS
SPI
POR, TIMING OSC, BAND GAP REF., OVER-VOLT. DET.
VPWR (VBATT) 14V D0 G0 D1 G1 D2 G2 D3 G3 D4 G4 D5 G5
PI0
PARALLEL/ SERIAL IN, SHIFT REG. CONTROL PARALLEL/ SERIAL IN, SHIFT REG. CONTROL PARALLEL/ SERIAL IN, SHIFT REG. CONTROL PARALLEL/ SERIAL IN, SHIFT REG. CONTROL PARALLEL/ SERIAL IN, SHIFT REG. CONTROL PARALLEL/ SERIAL IN, SHIFT REG. CONTROL
DATA LATCH
DRAIN MONITOR DRIVE CONTROL CHANNEL #0 GATE DRIVER DRAIN MONITOR DRIVE CONTROL CHANNEL #1 GATE DRIVER DRAIN MONITOR DRIVE CONTROL CHANNEL #2 GATE DRIVER DRAIN MONITOR DRIVE CONTROL CHANNEL #3 GATE DRIVER DRAIN MONITOR DRIVE CONTROL CHANNEL #4 GATE DRIVER DRAIN MONITOR DRIVE CONTROL CHANNEL #5 GATE DRIVER HIP0063
PI1
DATA LATCH
PARALLEL INPUTS
PI2
DATA LATCH
PI3
DATA LATCH
PI4
DATA LATCH
PI5
DATA LATCH
HLOS (SEL) HPW01 HPW45
HLOS
GND HARDWARE GENERATED OR CUSTOM LOGIC SOURCED PWM CONTROL SIGNAL INPUTS
2 - HIP0061 OR EQUIVALENT
FIGURE 1. TYPICAL APPLICATION CIRCUIT FOR THE HIP0063 SHOWING HOW THE GATE DRIVE OUTPUT AND DRAIN MONITOR INPUT CONTROLS TWO HIP0061 THREE FET ARRAYS
CS
SCK (CPOL = 0, CPHA = 1)
MSB
6
5
4
3
2
1
LSB
INTERNAL STROBE FOR DATA CAPTURE
FIGURE 2. SPI DATA AND CLOCK TIMING DIAGRAM. SERIAL COMMUNICATION IS INITIATED WHEN CS GOES LOW AND SCK IS LOW. 8 OR 16 BITS OF DATA IS CLOCKED INTO SI ON THE LEADING EDGE OF SCK. DATA IS CLOCKED OUT OF SO ON THE TRAIL EDGE OF SCK. WHEN CS GOES HIGH, DATA IS LATCHED TO CONTROL EACH CHANNEL
2
Specifications HIP0063
Absolute Maximum Ratings
Logic Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 7V Max Quiescent Logic Supply Current, ICC . . . . . . . . . . . . . . . . . 5mA Logic Input Voltage . . . . . . . . . . . . . . . . . . . . . . -0.3V to VCC + 0.3V System Supply Voltage Monitor, VPWR (Note 1) Max Continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.5V to 38V Max Drain Clamp Voltage, VDM (Note 2) . . . . . . . . . . . . . . . . . . 75V Max Gate Drive Output Voltage, VG (Note 3) . . . . -0.3 to VCC + 0.3V Operating Ambient Temperature Range, TA . . . . -40oC to +125oC Operating Junction Temperature Range . . . . . . -40oC to +150oC Storage Temperature Range, TSTG . . . . . . . . . . -55oC to +150oC Lead Temperature (Soldering 10s Max) . . . . . . . . . . . . . . . +265oC
Thermal Information (Typical)
Thermal Resistance 28 Lead SOIC Package . . . . . . . . . . . . . . . . . . . . . . . JA 75oC/W
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Electrical Specifications
PARAMETERS POWER SUPPLY Logic Supply Quiescent Current VCC Threshold for POR Reset
VCC = 4.5V to 5.5V, VPWR = 5.5V to 17V, TA = -40oC to +125oC, Unless Otherwise Specified SYMBOL CONDITIONS MIN TYP MAX UNITS
ICC VPOR PI0-5 High (ON), Increase VCC, Measure VCC Threshold When Gate Drive Goes High PI0-5 High, Decrease VCC, Measure VCC Threshold when Gate Drive goes Low, Hysteresis Equals Differential VCC Voltage for Gate Drive High to Gate Drive Low VPWR = 14V VPWR = 14V VPWR Threshold Measured When Gate Drive Voltage, VG Goes Low
3.5
4
5 4.25
mA V
POR Hysteresis
VPOR_HYS
-
500
-
mV
Undervoltage Lockout, Low VCC Battery Supply Monitor Current VPWR Over-Voltage Shutdown Threshold VPWR Over-Voltage Shutdown Hysteresis LOGIC INPUTS Input High Voltage; SI, SCK, CS Input Low Voltage; SI, SCK, CS Input Leakage Current; SI, SCK Input Pulldown Currents; PI0-5, HPW01, HPW45 Input Pullup Currents; CS, HLOS Threshold Voltage at Falling Edge, PI0-5, HLOS, HPW01, HPW45 Threshold Voltge at Rising Edge, PI0-5, HLOS, HPW01, HPW45 Input Hysteresis Voltage; PI0-5, HLOS, HPW01, HPW45 Input Capacitance, SCK, SI DATA OUTPUT SO Data Output High Voltage SO Data Output Low Voltage SO Three-State Leakage Current SO Three-State Capacitance
VCC IPWR VPWR_OVTH VPWR_OVHYS
1 30 -
2 35 1
3.7 150 40 -
V A V V
VIH VIL ILK IIN_PD IIN_PU VT VT + VIN_HYS CIN 0 < VIN < VCC 0.3VCC < VIN < VCC GND < VIN < 0.7 VCC
0.7VCC -10 3 -25 1.5 1.8 250 -
0 10 -10 2.2 2.6 500 7
0.3VCC 10 25 -2 3.0 3.4 650 12
V V A A A V V mV pF
VOH VOL ISOT CSOT
IO = 5mA Source Current IO = 5mA Sink Current VCC = 0V to 5.5V 0 < VIN < VCC
0.8VCC -10 -
0.2 1 15
0.4 10 20
V V A pF
3
Specifications HIP0063
Electrical Specifications
PARAMETERS GATE DRIVE OUTPUT Gate Drive Output Source Current Gate Drive Output Sink Current Gate Drive Rise Time with Load Output Turn-ON Delay, Rising Edge of CS to 10% of VG Turn-ON Output Turn-OFF Delay, Rising Edge of CS to 10% of VG Turn-OFF IGOH IGOL tR tPHL tPLH VG = 0V VG = 4.5V Cap. Load, Gate to GND = (TBD)pF -4.4 0.2 TBD TBD 5 5 -0.5 3.3 10 10 mA mA s s s VCC = 4.5V to 5.5V, VPWR = 5.5V to 17V, TA = -40oC to +125oC, Unless Otherwise Specified (Continued) SYMBOL CONDITIONS MIN TYP MAX UNITS
DRAIN MONITOR INPUT AND PROTECTION D0-5 Drain Monitor Clamp Voltage VDM D0-5 Clamp Current, IDM = 2mA; tPW =100s, Duty Cycle <1%, Gate Drive Voltage, VG Low (Note 2) 0.3VCC < VDM < VCC 58 64 74 V
D0-5 Drain Monitor Pulldown Current Sink Fault Threshold Voltage Sensed at the Drain Monitor Input, Shorts/Opens Short Circuit Sense Fault Time VDM > VDM_FTH, Gate ON/High Over-Current Refresh Time During Short Circuit (Gate Drive OFF) Over-Current ON Time Duty Cycle Open-Load "OFF" Sense Time VDM < VDM_FTH, Gate OFF/Low
IDM VDM_FTH tSC_ON
3 0.3VCC
10 0.4VCC 28 28 16.4 16.4 0.34 28
25 0.5VCC 39 36 21.4 19.6 0.37 39
A V s s ms ms % s
TA = -40oC to 25oC TA = 25oC to 150oC 25oC
18 19 11.4 12.0 0.31 18
tSC_REF
TA = TA =
-40oC 25oC
to
to
150oC
Duty Cycle = tSC/(tSC + tREF) tOL_OFF
NOTE: 1. Refer the Figure 3 recommended application circuit for VPWR protection given system power supply conditions of +24V for double battery voltage, -14V for reverse battery voltage and +80V system level load dump voltages. 2. VDM refers to the specified Drain Monitor voltage input at pins D0 thru D5, that monitor the drain status from the respective external MOSFET. 3. VG refers to the specified Gate Drive voltage at the output pins, G0 thru G5, that drive the Gate of the respective external MOSFET.
+5V 0.01F VCC PI0 PI1 PI2 PI3 PI4 PI5 CS SI SCK SO HLOS HPW01 HPW45 VPWR D0 G0 D1 G1 G2 D2 D3 G3 G4 D4 G5 D5 GND 0.01F
27V 0.01F LOAD: 13, 6.8H ONE OF SIX OUTPUTS
VBATT
HIGH SPEED PARALLEL DATA INPUT
CHIP SELECT SPI BUS SERIAL INPUT PWM SELECT HARDWARE GENERATED PWM INPUT
FIGURE 3. TYPICAL APPLICATION CIRCUIT FOR THE HIP0063 SHOWING THE VPWR SUPPLY INTERFACE WITH CIRCUIT PROTECTION COMPONENTS. FOR THE VALUES SHOWN, GIVEN A LOAD DUMP OF 80V THAT DECAYS TO THE VPWR LEVEL IN 350ms, THE 27V ZENER DIODE IS REQUIRED TO CLAMP THE TRANSIENT TO 60V MAXIMUM. FOR THE REVERSE BATTERY PROTECTION, THE ZENER DIODE CLAMPS NEGATIVE VOLTAGES
4
Specifications HIP0063
Serial Peripheral Interface Timing
PARAMETERS Clock Operating Frequency Clock Period Clock High Time Clock Low Time Falling Edge of CS to Rising Edge of SCK Falling Edge of SCK to Rising Edge of CS SI to SCK Setup Time (See Figure 4) SYMBOL fSCK tSCK tWH tWL tLEAD tLAG tSU2 CL = 200pF SCK = 0.8V to 0.8V SCK = 2V TO 2V; fSCK = 1.8MHz SCK = 0.8V TO 0.8V; fSCK = 1.8MHz CS = 0.8V to SCK = 2V SCK = 0.8V to CS = 2V SI = 0.8, 2V to SCK = 2V; fSCK = 2.25MHz SCK = 2V to SI Hold CL = 200pF CL = 200pF SO = 0.8, 2V to SCK = 0.8V; CL = 200pF SO = 0.8, 2V to SCK = 0.8V; CL = 200pF CL = 200pF CL = 200pF CS = 0.8V to SO Low Impedance TEST CONDITION MIN 1.8 TYP 4 250 100 100 150 50 25 MAX 555 248 248 200 200 55 UNITS MHz ns ns ns ns ns ns
SI Hold After SCK Rise Rise Time of Incoming Signals Fall Time of Incoming Signals SO Data Valid to Falling Edge of SCK Falling Edge of SCK to SO Rise Time of SO Fall Time of SO Falling Edge of CS to SO Operational (1k Pulldown on SO Pin) Rising Edge of CS to SO Three-State (1k Pulldown on SO Pin) Rising Edge of SCK to SO (Data Valid)
tH2 trSI tfSI tSU1 tH1 trSO tfSO tSOEN
80 80 -
10 125 30 30 150
55 120 120 50 50 300
ns ns ns ns ns ns ns ns
tSODIS
CS = 2V to SO Three-State
-
150
200
ns
tVALID
CL = 200pF, 1.8MHz CL = 200pF, 2.25MHz 172 117 ns ns
CS
tSCK tLEAD 1 2 tWL tVALID tSU2 (MSB = 0) tH2 LSB tWH X tLAG
SCK
SI
tSODIS LAST BIT XMITTED tSOEN
SO
MSB tSU1 tH1
LSB
FIGURE 4. TIMING DIAGRAM FOR THE HIP0063 SHOWING THE SPI BUS INPUT CONTROL SIGNALS
5
HIP0063 Applications
Input Control The application circuit for the HIP0063 is shown in Figure 1 while details of input control are shown in the block diagram. Gate control and diagnostic fault management are provided for each of six channels. Gate controlled switching is OR'd by the SPI Bus microcontroller interface or the independent parallel logic inputs (PI0-1) as a user option. The six control channels provide gate drive (G0-5) for the MOS output drivers while detecting fault conditions at each output via the drain monitor pins (D0-5). An HLOS input control overrides the serial input and modifies the parallel operation. SI (serial input) data from a SPI controller is clocked into the input register on the positive leading edge of the clock pulse, SCK while CS is low. (Data is clocked from the SO output on the trailing edge of the SCK clock pulse.) Either 8-bit or 16-bit control may be used. The input data is clocked MSB first and all unused bits should be low. Detailed information on the bit structure for both 8-bit and 16-bit operation is shown in Table 1. A special feature of the HIP0063 is a PWM mode of operation set by a high on the HLOS pin. This mode is primarily used to control fuel injectors and allows direct access to control channels 0 and 1 from the HPW01 Pin and channels 4 and 5 from the HPW45 Pin. When HLOS is high, the serial input is disabled and SO goes to three-state. Channel#2 and Channel#3 are independently controlled from the parallel input during the HLOS/PWM operation. A pullup is needed on the SO pin to keep the SO output high when HLOS/PWM is active. Fault Protection Output fault conditions are monitored at the Drain Monitor pin, DO. Feed back of the fault condition is returned by the SPI SO data output when new data is clocked by SCK into the SI data input. Output Load Short conditions are detected at the drain monitor pin when the Output is ON and the drain voltage is greater than the specified VDM_FTH voltage threshold for a time greater than tSC_ON . When the output load short is detected, the output goes to a low duty cycle mode. The duty cycle is a ratio of the ON time required to sense and enter the low duty cycle mode (tSC_ON) and the following refresh OFF time, tSC_REF. Open Load fault conditions are detected when the Output is OFF and the drain voltage falls below the VDM_FTH threshold level for a time greater than tOL_OFF . If the Output is ON, Open Load faults will not be detected. For Load Short and Open Load fault conditions, a fault bit with a logic state of "1" is placed in the respective fault register. If the fault is terminated, the bit returns to "0". When CS goes low for serial communication, all fault bits are latched. Fault data is read at SO when CS is low and SCK is clocked. When CS goes high, new data may enter the fault register. The VPWR pin monitors the supply voltage (battery supply) for over-voltage fault conditions. Over-voltage protection shuts down all output drivers when the over-voltage threshold of typically 35V is detected at the VPWR pin. If the VCC supply is low or off, VPWR supplies the necessary bias to switch off all output gates. Each output of the HIP0063 has a drain-to-gate zener diode clamp to limit peak voltage at the drain of the output drivers. The voltage pulse from switched inductive loads is clamped when the drain-to-gate zener forces the output driver into conduction. The MOSFET drain-to-source output clamp voltage level is typically 67V. Diagnostic Feedback Normal operation in the SPI mode calls for bits 0 thru 5 to be sent as a "1" to control turn-on. Bit 6 is always low (reserved for use as a test bit) and bit 7 should be low to provide a flag for HLOS/ PWM operation. When there is no fault condition, the return bits from SO will be the same as the bits sent. Fault conditions return the XOR complement. When the complement is received, it may also indicate an error in communication or HLOS/PWM controlled operation has occurred. A CPU instruction to send the last command will verify HLOS action. After the HLOS action is terminated, resending the previous command will verify normal opera-
TABLE 1. SPI DATA FORMAT - BIT DEFINITION FOR DATA INPUT AND OUTPUT
8-BIT MODE: 7 MSB 6 5 4 3 2 1 0 LSB
Bits 0 to 5: Bit 6: Bit 7: Note:
16-BIT MODE: 15 MSB 14
Turns-ON the corresponding output gate when set HIGH. Not used, set LOW (Reserved as a test bit). Bit 7 can be used as an HLOS flag. Always set LOW. If the complement is returned, then HLOS is active. (i.e., HLOS forces SO into a three-state mode and a HIGH will be returned). Fault Bits clocked out when data clocked in.
13
12
11
10
9
8
7
6
5
4
3
2
1
0 LSB
Bits 0 to 5: Bit 6: Bit 7: Bits 8 to 13: Bit 14: Bit 15:
Turn-ON the corresponding channel output gate when set HIGH and will always be returned as sent. Not used, set LOW. (Reserved as a test bit). Not used, (Will be returned as sent). Fault bits for outputs 0 to 5 respectively. Returned as sent or returned as the complement to indicate an output fault. Not used, (Will be returned as sent). HLOS bit, (See bit 7 for the 8-bit mode).
6
HIP0063
tion. If there is still a problem in verifying the data sent, a communication error and further diagnosis is required. If the 16bit mode is used, the data sent in the first byte should be the same as the data received in the second byte. CS Chip Select (Enable) Pin for the SPI interface The CS Chip Select is an active low input pin. SPI bus communication with the master device becomes active when CS is switched low. When CS is active low, data may then be shifted into SI and out of SO with each SCK clock pulse. When CS goes high, the SO output switches to three-state and SPI communication is terminated. When CS goes active low, fault bits in the internal fault register are latched (with no further change during data transmission). When CS goes high, the fault status register is then open to new fault information. The CS input is a CMOS logic level output with an internal active pullup. PI0 Thru PI5 Parallel Inputs Each gate control channel has an OR'd input for control of the Gate Drive output. The control bits from the SPI input are OR'd with the respective parallel input control bit. Turn-on control for each channel may be initiated either from the SPI control input or the independent parallel input. Each PIx input has CMOS logic level control with an internal active pulldown and must be switched high to turn-on the Gate Drive output. (Refer to the Input Control section of Applications for further details on transfer of control with HLOS/PWM switching). HLOS, HPW01, HPW45 Pins The HLOS pin is switched high by an I/O select line to initiate PWM operation using the HPW01 and HPW45 pins. When active, the SPI inputs and the PI0, PI1, PI4 the PI5 parallel inputs are disabled. The channels 0 and 1 are under the direct control of the HPW01 pin and channels 4 and 5 are under the direct control of the HPW45 pin. Channels 2 and 3 have direct and independent control by the PI2 and PI3 inputs. These pins have CMOS logic level control. The HLOS pin has an internal active pullup and the HPW01 and HPW45 have internal active pulldowns. The state of the HPW01 and HPW45 pins are "don't care" when the HLOS pin is low. Go Thru G5 Gate Drive Pins The Gate Drive pins each drive external NDMOS or equivalent MOSFETs to provide low side switching control of the output loads. The Gate Drive pins are switched high to turn-on the MOSFET output. The Gate Drive output is switched to a low duty cycle mode during over-current fault conditions or switched low during low VCC POR reset conditions. D0 Thru D5 Drain Monitor Pins The Drain Monitor input pins sense an over-current fault at the drain of the output MOSFET driver by detecting the drain voltage to be higher than an internal voltage reference when the output is on. Open Load conditions are sensed at the Drain Monitor input when the output is off by detecting the drain voltage of the MOSFET to less than in internal reference. For each channel, a single fault bit is returned for either condition. For each channel, an internal zener diode connects the Drain Monitor input to the Gate Drive output to provide voltage clamping when an inductive load is switched off. When the drain to gate zener diode conducts, the gate is turned-on sufficiently to clamp the inductive kick voltage pulse.
Pin Descriptions
VCC - Logic Level Power Supply Pin The VCC pin is the primary power supply input to the IC with a +5V logic level voltage. The normal operating voltage range is 4.5V to 5.5V. At turn-on and when VCC is less than the POR Threshold, the POR forces a reset which turns-off the Gate Drive outputs. VPWR - Battery Voltage Level Power Supply Monitor Pin All MOSFETs are normally controlled by the HIP0063 and are separately biased by a Battery or System level power supply. The VPWR pin monitors the Battery/System Power Supply and forces over-voltage shutdown under excessive high voltage conditions by forcing all Gate Drive outputs low. The VPWR input also supplies the necessary bias under low VCC reset conditions to switch off the Gate Drive output. GND Pin The GND (Ground) pin is the 5V logic supply ground for the IC and is a common ground for all functions on the chip. SCK SPI Clock Pin SCK is the bit shift clock input of the SPI interface and is connected to the SCK pin of the master device. Available control bits are clocked into the SI serial data input on the rising edge of the SCK pulse. SCK is low when CS goes active low. Each rising edge transition shifts in 1 bit of data. The SCK clock pulse has a 50% duty cycle and a CMOS logic level. The negative edge transition of SCK shifts available data out of the SO data output pin. SI Serial Data In Pin SI is the Serial Data Input pin of the SPI interface and receives command data from the master device on the rising edge of SCK when CS is low. Six Gate Drive control bits and the HLOS monitor bit are contained in the serial data byte at the SI input. The SI data input is an 8-bit or 16-bit control byte sent MSB first. (Refer to Table 1 for bit information.) Outputs are switched on with "1" state. Unused bits, including the HLOS bit, are set to the "0" state. This is a CMOS logic level input with an internal active pulldown. SO Serial Data Out Pin SO is the Serial Data Output pin of the SPI interface and transmits control status and fault data to the master device. The SO Serial Data Output is switched to an active state while CS is low and three-states when CS is high or HLOS is active. Otherwise, this is a CMOS logic level output with available data shifted out at SO on the negative edge of the SCK clock pulse. The normal SO output data is the same as the SI input data and is returned MSB first. If any of the channels are returning fault bits, the respective bit will be returned as a complement. If the HLOS control mode is active, the HLOS bit is returned as a complement. (Refer to Table 1 for bit information. Refer to the Input Control section of Applications for further details on transfer of control with HLOS/PWM switching).
7
HIP0063 Small Outline Plastic Packages (SOIC)
N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45o H 0.25(0.010) M BM
M28.3 (JEDEC MS-013-AE ISSUE C)
28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A A1
L
MILLIMETERS MIN 2.35 0.10 0.33 0.23 17.70 7.40 MAX 2.65 0.30 0.51 0.32 18.10 7.60 NOTES 9 3 4 5 6 7 8o Rev. 0 12/93
MIN 0.0926 0.0040 0.013 0.0091 0.6969 0.2914
MAX 0.1043 0.0118 0.0200 0.0125 0.7125 0.2992
B C D E
A1 0.10(0.004) C
e H h L N
0.05 BSC 0.394 0.01 0.016 28 0o 8o 0.419 0.029 0.050
1.27 BSC 10.00 0.25 0.40 28 0o 10.65 0.75 1.27
e
B 0.25(0.010) M C AM BS
NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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